1. Field
This disclosure relates generally to integrated circuits, and more specifically, to memory cells that use a fin as a channel and have a floating gate.
2. Related Art
Typical non-volatile memories (NVMs) have layer of storage material, which is commonly a floating gate of polysilicon, that is between a channel and a control gate. The NVM can be programmed and erased by moving electrons or holes to and from the floating gate. A common technique is for the charge to move between the channel side and the floating gate for both program and erase. In order to achieve the charge transfer there must be enough voltage between the floating gate and the channel side regardless of the particular technique chosen such as hot carrier injection or tunneling. A voltage cannot be applied directly to the floating gate because it is floating so the voltage at the floating gate is induced by the voltage between the control gate and the channel. The voltage on the floating gate is controlled by voltage division between the floating gate to channel capacitance and the floating gate to control gate capacitance. Thus for programming and erasing it is desirable for the floating gate to control gate capacitance to be large compared to the floating gate to channel capacitance. For reading the state of the memory cell, however, it is desirable for the floating gate to channel capacitance to be high. Thus increasing the ratio of the floating gate to control gate capacitance to the floating gate to channel capacitance is not likely to be possible by reducing the floating gate to channel capacitance. Thus, the voltage on the control gate may need to be quite high in order to achieve the needed voltage on the floating gate. This places further requirements on the memory cell and in particular the insulating layer between the control gate and the floating gate.
Thus there is a need to improve the ratio of the floating gate to control gate capacitance to the floating gate to channel capacitance while not requiring a reduction in the capacitance of the floating gate to channel capacitance.